发明名称 BUS INTERFACE WRAPPER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a circuit scale of a bus interface wrapper circuit by allowing an AHB-Lite master to be built in an AHB bus system in the same manner as an AHB master without providing local arbiters per AHB slave. SOLUTION: A wrapper circuit 1-1 is added to an AHB-Lite master 4-5. The wrapper circuit 1-1 sends a signal showing a state of being not capable of receiving data, to the AHB-Lite master when receiving a data transfer request from the AHB-Lite master and temporarily holds transfer data, and during this period, the wrapper circuit issues an access request signal to an arbiter 2-4 and transfers data to an AHB slave 4-4 through a selector 4-3 in response to reception of an access permission signal. The wrapper circuit ceases to issue the access request signal to the arbiter and transmits a data transfer completion signal to the AHB-Lite master, in response to reception of a data transfer completion signal from the AHB slave. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007219968(A) 申请公布日期 2007.08.30
申请号 JP20060041889 申请日期 2006.02.20
申请人 FUJITSU LTD 发明人 KIUCHI SHUSUKE;KADOSAWA TAKASHI;ISHIMORI TORU
分类号 G06F13/36 主分类号 G06F13/36
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