发明名称 |
METHOD AND CIRCUIT FOR FAST FOURIER TRANSFORM |
摘要 |
A method for FFT/IFFT computation, comprising: identifying whether grouping data is needed based on data bitwidth distribution in a set of data, wherein the set of data includes data in a stage of a FFT/IFFT computation; assigning different data representations including effective bit and group index for data identified in different groups if grouping is needed, wherein data in a group have same exponent, and data in different groups have different exponents; and outputting a signal indicating the exponent; for each of a plurality of short sequence FFT/IFFT computation—decomposing data used in present short sequence FFT/IFFT computation into at least a first multi-bit part and a second multi-bit part; respectively calculating FFT/IFFT computation results for the first multi-bit part and the second multi-bit part; adding the FFT/IFFT computation results for the first and the second multi-bit part; scanning a plurality of short sequence FFT/IFFT computation added results. |
申请公布号 |
US2016226695(A1) |
申请公布日期 |
2016.08.04 |
申请号 |
US201514679014 |
申请日期 |
2015.04.05 |
申请人 |
Montage Technology (Shanghai) Co., Ltd. |
发明人 |
Song Heming |
分类号 |
H04L27/26 |
主分类号 |
H04L27/26 |
代理机构 |
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代理人 |
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主权项 |
1. A method for Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) computation, comprising:
identifying whether grouping data is needed based on data bitwidth distribution in a set of data, wherein the set of data includes data in a stage of a FFT/IFFT computation; assigning different data representations including effective bit and group index for data identified in different groups, if grouping the data is needed, wherein data in a group have same exponent, and data in different groups have different exponents; and outputting a signal indicating the exponent; for each of a plurality of short sequence FFT/IFFT computation
decomposing data used in present short sequence FFT/IFFT computation into at least a first multi-bit part and a second multi-bit part, with the first multi-bit part higher than the second multi-bit;respectively calculating FFT/IFFT computation results for the first multi-bit part and the second multi-bit part;adding the FFT/IFFT computation results for the first multi-bit part and the second multi-bit part; scanning a plurality of short sequence FFT/IFFT computation added results, wherein the plurality of short sequence FFT/IFFT computation comprises FFT/IFFT computation in a stage. |
地址 |
Shanghai CN |