发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 A semiconductor memory device includes memory cells, word lines that are electrically connected to gates of the memory cells, a source line that is electrically connected to one end of the memory cells, and a controller that executes a read operation over first, second, third, and fourth time periods. A first voltage is applied to a selected word line during the first and second time periods of the first operation, and a second voltage that is higher than the first voltage is applied to the selected word line during the third and fourth time periods of the second operation. A third voltage is applied to the source line during the first and third time periods, and fourth and fifth voltages that are lower than the third voltage are applied to the source line during the second and fourth time periods, respectively.
申请公布号 US2016276034(A1) 申请公布日期 2016.09.22
申请号 US201615061960 申请日期 2016.03.04
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MAEJIMA Hiroshi
分类号 G11C16/26;G11C29/52;G11C16/04;G06F11/10;G11C16/10;G11C16/08 主分类号 G11C16/26
代理机构 代理人
主权项 1. A semiconductor memory device comprising: a plurality of memory cells that are stacked above a substrate; a plurality of word lines that are electrically connected to gates of the memory cells; a source line that is electrically connected to one end of the memory cells; and a controller configured to execute a read operation that includes a first operation carried out over first and second time periods and a second operation carried out over third and fourth time periods, a first voltage being applied to a selected word line during the first and second time periods of the first operation, a second voltage that is higher than the first voltage being applied to the selected word line during the third and fourth time periods of the second operation, a third voltage being applied to the source line during the first and third time periods, a fourth voltage that is lower than the third voltage being applied to the source line during the second time period, and a fifth voltage that is lower than the third voltage being applied to the source line during the fourth time period.
地址 Tokyo JP