| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generator (SSCG) capable of sufficiently reducing EMI without increasing its circuit scale. <P>SOLUTION: The SSCG has a PLL (phase locked loop) circuit 1 for generating a clock signal, and a frequency converting circuit 2 for executing frequency conversion of the clock signal. The frequency converting circuit 2 has a counter 11, set registers 12, 13, a multiplexer 14, a 1/P frequency divider 15, a latch register 16, an up-down counter 17, a set register 18, and an adder 19. Since a modulation profile in which modulation points per relative time obtained by dividing one period of a Hershey-kiss modulation profile into eight are connected using straight lines is used to change a frequency division ratio of a 1/N frequency divider 8 eight times in one period, frequency modulation equivalent to the Hershey-kiss modulation profile can be carried out without providing a characteristic table for the Hershey-kiss modulation profile. <P>COPYRIGHT: (C)2009,JPO&INPIT |
