发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is "1", output signals of a first AND circuit and a second AND circuit are fixed to a low level and an output of an OR circuit is fixed to a high level. Therefore, output signals of fourth through sixth flip-flops FF4-FF6 are not transferred to first through third analog circuits during the scan test. On the other hand, the output signals of the fourth through sixth flip-flops FF4-FF6 are transferred to the first through third analog circuits during a normal operation.
申请公布号 US2009106610(A1) 申请公布日期 2009.04.23
申请号 US20080246873 申请日期 2008.10.07
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR CO., LTD. 发明人 NISHIYAMA TAKAKO;ITO HIDEO
分类号 G01R31/3177;G06F11/25 主分类号 G01R31/3177
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