LOW VOLTAGE DIFFERENCE OPERATED EEPROM AND OPERATING METHOD THEREOF

摘要

The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.

主权项

1. An operating method for a low voltage difference-operated EEPROM, wherein said low voltage difference-operated electrically erasable programmable read only memory comprises a semiconductor substrate and at least one transistor structure formed in said semiconductor substrate, and wherein said transistor structure includes a first electric-conduction gate and at least two first ion-doped regions formed inside said semiconductor substrate and located at two sides of said first electric-conduction gate to function as a source and a drain, and wherein regions of said first ion-doped regions, which are near an interface of said source and said first electric-conduction gate and an interface of said drain and said first electric-conduction gate,are further implanted with the same type of ions to increase an ion concentration of said regions of said first ion-doped regions, and wherein said method comprises a step:
respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to said first electric-conduction gate, said source, said drain and said semiconductor substrate, wherein while said transistor structure is an N-type transistor structure, in writing, Vsub=ground, Vs=Vd≧0, and Vg=HV (High Voltage), or Vsub=ground Vs=Vd=HV, and Vg>2V, in erasing, Vsub=ground, Vs=Vd=HV, and Vg=0, a floating voltage, or <2V and wherein while said transistor structure is a P-type transistor structure, in writing, Vsub=HV (High Voltage), Vs=Vd≦HV, and Vg=0, or Vsub=HV, Vs=Vd=0, and Vg is smaller than HV=2V, in erasing, Vsub=HV, Vs=Vd=0, and Vg is a floating voltage or smaller than HV=2V.