| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a memory cell array which can suppress the variation of an electric current value at a bit line output location not depending on the location of a memory cell from which information is read, while suppressing power consumption and a time required for the charge or discharge of the bit line to low and short when information is read from the memory cell. <P>SOLUTION: In the memory cell array, one pair of drain and source selectors connected to one end of a sub bit line and the other pair of drain and source selectors connected to one end of the other sub bit line are disposed on opposite sides, respectively, with a word line therebetween. Both sub bit lines are adjacent. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
