Serial-to-parallel- and parallel-to-serial converter

摘要

A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiming section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.