发明名称 シミュレーション装置,方法,およびプログラム
摘要 A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent instruction as the execution time of the externally-dependant instruction.
申请公布号 JP5961971(B2) 申请公布日期 2016.08.03
申请号 JP20110224714 申请日期 2011.10.12
申请人 富士通株式会社 发明人 桑村 慎哉;池 敦
分类号 G06F9/455 主分类号 G06F9/455
代理机构 代理人
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