Dynamic burst length output control in a memory

摘要

A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

主权项

1. A memory device comprising:
a plurality of latches configured to latch burst length control data; a first counter, coupled to the plurality of latches, configured to generate a latch signal to each of the plurality of latches; a second counter, coupled to the plurality of latches, configured to generate an output enable signal to each of the plurality of latches; a first circuit coupled to the first counter and the plurality of latches and configured to generate a first clock signal for the first counter responsive to latency delays of the memory device, the first circuit further configured to store the burst length control data; and a second circuit coupled to the second counter and configured to generate a second clock signal for the second counter responsive to a received command and the latency delays of the memory device.