发明名称 DISPLAY CONTROLLER FOR GAME MACHINE
摘要 PROBLEM TO BE SOLVED: To raise the transfer rate of data when a buffer means is arranged between an LSI for image processing and a data storage means in a display controller for a game machine. SOLUTION: When a VDP 134 continuously outputs an address signals a plurality of times in order to call image data having a size not to be output by one-time data signal, from a character ROM 136, the VDP 134 outputs the address signal Address (1), and then outputs the succeeding address signal Address (1) before a data acquisition time of the preceding address signal elapses. The VDP 134 outputs the succeeding address signal Address (1), and then acquires a data signal Data (4) based on the preceding address signal Address (1). Consequently, the transfer rate is raised by shortening a transfer time by one-page unit for the portion of a delay time generated in a level shifter 200. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008220584(A) 申请公布日期 2008.09.25
申请号 JP20070062293 申请日期 2007.03.12
申请人 DAIKOKU DENKI CO LTD 发明人 FUJISAWA MAKIO
分类号 A63F7/02 主分类号 A63F7/02
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