发明名称 PROCESSOR AND OBJECT CODE GENERATION APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a processor capable of identifying the end of a very long instruction word of a variable instruction length without being influenced by the maximum number of instructions constituting the very long instruction word. SOLUTION: The processor 101 includes: instruction registers 114f to 114i capable of individually recording four instructions; operation units 115a to 115d individually corresponding to the instruction registers 114f to 114i to execute an instruction issued from each corresponding instruction register; and a very long instruction word analysis part 114d for analyzing a very long instruction word, and when an issue control instruction for issuing an instruction is included in the very long instruction word, controlling the instruction registers 114f to 114i, issuing instructions excluding the issue control instruction out of instructions constituting the very long instruction word to the operation units 115a to 115d in parallel, and when the issue control instruction is not included, issuing four instructions constituting the very long instruction word to the operation units 115a to 115d in parallel. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008090744(A) 申请公布日期 2008.04.17
申请号 JP20060273275 申请日期 2006.10.04
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAZAKI MASAYUKI
分类号 G06F9/32;G06F9/38 主分类号 G06F9/32
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