发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT METHOD, AND RECORDING MEDIUM WITH THE METHOD RECORDED
摘要 PROBLEM TO BE SOLVED: To evaluate effects of parasitic elements caused between a semiconductor integrated circuit and a carrier substrate in a design stage. SOLUTION: An analytical model to be analyzed in a design stage of a semiconductor integrated circuit is not closed only in the semiconductor integrated circuit, but an analytical model including a circuit substrate mounted with the semiconductor integrated circuit and parasitic elements between the circuit substrate and the semiconductor integrated circuit as well as the semiconductor integrated circuit is generated and analyzed to evaluate effects of the parasitic elements caused between the semiconductor integrated circuit and a carrier substrate in the design stage. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006344111(A) 申请公布日期 2006.12.21
申请号 JP20050170631 申请日期 2005.06.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAYAMA TAKESHI;SAITO YOSHIYUKI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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