| 摘要 |
<p>A data compression and display memory apparatus which is capable of obtaining a better compression efficiency by using a DPCM and a line interpolation technique and providing a simple hardware construction. The apparatus includes a DPCM and quantization unit for quantizing 8-bit luminance signal Y and chrominance signal C, which is an ODD field signal, in accordance with a clock signal CK1 from the control signal generator for thus outputting 4-bit luminance signal Y and chrominance signal C, a bit converter for converting quantized 4-bit luminance signal Y and chrominance signal into 8-bit, respectively, a memory for storing an output from the bit converter in accordance with read/write signals RD and WR from the control signal generator, a bit converter for converting 8-bit luminance signal Y and chrominance signal C from the memory into 4-bit, respectively, a reverse DPCM and dequantization unit for reverse-DPCM-processing and dequantizing an output from the bit converter in accordance with the clock signal CK1 and outputting an ODD field signal, an interpolation unit for generating an EVEN field signal from the ODD field signal from the reverse DPCM and dequantization unit in accordance with the clock signal CK1, and a multiplexor for multiplexing the ODD field signal and EVEN field signal in accordance with a control signal CT from the control signal generator and outputting 8-bit luminance signal Y and chrominance signal C. <IMAGE></p> |
