| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device for improving the precision of failure analysis by detaledly discussing validity and effectiveness of a test pattern in practical chips, and to provide its failure analysis method. SOLUTION: The semiconductor device and its failure analysis method include pseudo-failure generation circuits 12a-12c for selectively outputting (OUT) a pseudo-failure signal for achieving an input signal IN from the normal circuit or prescribed failure to a normal circuit in a pseudo manner, on the basis of control signals F1-F3 and an activation signal FE input from the outside; and a control signal generation circuit 11 for outputting to the pseudo-failure generation circuits 12a-12c by initialization-setting the control signals F1-F3, when it is reset, on the basis of a selection reference signal SD from the outside. COPYRIGHT: (C)2007,JPO&INPIT
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