HIGH PERFORMANCE ISOLATED VERTICAL BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FORMING IN A CMOS INTEGRATED CIRCUIT

摘要

A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

主权项

1. A method of forming an integrated circuit, comprising the steps of:
providing a substrate comprising a p-type semiconductor material, said substrate including an area for an NMOS transistor, an area for a PMOS transistor, an area for an isolated n-channel DEMOS transistor, and an area for an isolated vertical PNP transistor; concurrently forming a first shallow n-type well surrounding said isolated n-channel DEMOS transistor, a second shallow n-type well surrounding said isolated vertical PNP transistor, and third shallow n-type well providing a body region for said PMOS transistor of said integrated circuit; concurrently forming a first deep n-type well underlying said isolated n-channel DEMOS transistor and a second deep n-type well underlying said isolated vertical PNP transistor, so that said first shallow n-type well connects with said first deep n-type well so as to isolate said isolated n-channel DEMOS transistor from said p-type semiconductor material of said substrate, and said second shallow n-type well connects with said second deep n-type well so as to isolate said isolated vertical PNP transistor from said p-type semiconductor material of said substrate; concurrently forming a first upper n-type layer providing an extended drain of said isolated n-channel DEMOS transistor and a second upper n-type layer providing a base of said isolated vertical PNP transistor; and concurrently forming a first lower p-type layer below said first upper n-type layer and a second lower p-type layer below said second upper n-type layer, said second lower p-type layer providing a collector of said isolated vertical PNP transistor.