发明名称 INTERFACE CIRCUIT INCLUDING BUFFER CIRCUIT FOR HIGH SPEED COMMUNICATION, SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME
摘要 A buffer circuit may include an amplification unit and an active load unit. The amplification unit is electrically coupled to an output node and configured to sense and amplify first and second signals. The active load unit is configured to form a peak of a signal outputted from the output node when the signal transitions.
申请公布号 US2016254814(A1) 申请公布日期 2016.09.01
申请号 US201514742922 申请日期 2015.06.18
申请人 SK hynix Inc. 发明人 HWANG Kyu Dong
分类号 H03K19/00;H03K19/0185 主分类号 H03K19/00
代理机构 代理人
主权项 1. A buffer circuit comprising: an amplification unit electrically coupled to an output node and configured to sense and amplify first and second signals; and an active load unit configured to form a peak of a signal outputted from the output node when the signal transitions.
地址 Icheon-si Gyeonggi-do KR