| 发明名称 |
Configurable Mailbox Data Buffer Apparatus |
| 摘要 |
A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers. |
| 申请公布号 |
US2016371200(A1) |
申请公布日期 |
2016.12.22 |
| 申请号 |
US201615184789 |
申请日期 |
2016.06.16 |
| 申请人 |
Microchip Technology Incorporated |
发明人 |
Catherwood Michael;Mickey David;Kris Bryan |
| 分类号 |
G06F13/10;G06F13/20;G06F13/42;G06F13/16 |
主分类号 |
G06F13/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A single chip microcontroller comprising a master core and a slave core, wherein the master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively, further comprising a communication interface between the master microcontroller and the slave microcontroller, wherein the communication interface comprises a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers. |
| 地址 |
Chandler AZ US |
