发明名称 配線基板の製造方法
摘要 PROBLEM TO BE SOLVED: To miniaturize and simplify a circuit board by acquiring a manufacturing technique of circuit boards capable of deriving the number of specific electrode pads to be disposed in a DUT (Device Under Test) part when the number of internal wiring layers of the circuit board are fixed and, thereby deriving the minimum number of internal wiring layers to be required when a predetermined number of specific electrode pads are disposed in the DUT part.SOLUTION: When the number of specific internal wiring layers is A, the number of columns of a plurality of surface electrode pads disposed in each DUT part is N, and the number of specific surface electrode pads to be disposed in each DUT part is B, the number B of the specific surface electrode pads satisfies the following relational expression: B<(X+1)×A (where X is a natural number from 1 to N).
申请公布号 JP6030291(B2) 申请公布日期 2016.11.24
申请号 JP20110172261 申请日期 2011.08.05
申请人 日本特殊陶業株式会社;トヨシマ電機株式会社 发明人 鈴木 健司;秋田 和重;大野 強
分类号 G01R1/073;G01R1/06;G01R31/26;H01L21/66 主分类号 G01R1/073
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