发明名称 |
Manufacturing method of semiconductor integrated circuit device |
摘要 |
A solid-state imaging element has problems of occurrence of dark current due to influences of an interface state at an interface between a semiconductor and an insulating film, e.g., between silicon and silicon oxide, and of charges generated in a device manufacturing process, which leads to signal noise, thereby degrading the function of a device, specifically, the imaging quality. The outline of the invention in the present application relates to a manufacturing method of a semiconductor integrated circuit device with a surface-irradiation type image sensor, which includes irradiating a main surface of a semiconductor wafer with photodiodes formed therein, with far-ultraviolet ray after forming a lowermost wiring layer of a multi-layer wiring and before forming a color filter layer, and then applying a heat treatment to the wafer. |
申请公布号 |
US9530819(B2) |
申请公布日期 |
2016.12.27 |
申请号 |
US201514797099 |
申请日期 |
2015.07.11 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
Maekawa Kazuyoshi |
分类号 |
H01L21/00;H01L27/146 |
主分类号 |
H01L21/00 |
代理机构 |
McGinn IP Law Group, PLLC. |
代理人 |
McGinn IP Law Group, PLLC. |
主权项 |
1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) providing a semiconductor wafer with numerous chip regions, the semiconductor wafer having numerous photodiodes formed in a matrix at a semiconductor region in a first main surface of the semiconductor wafer in each of the chip regions so as to configure a surface-irradiation type image sensor; (b) after the step (a), forming a multi-layer wiring layer over the first main surface of the semiconductor wafer; and (c) after the step (b), forming a color filter layer over the multi-layer wiring layer, wherein the step (b) comprises sub-steps of: (b1) forming a first wiring layer included in the multi-layer wiring layer; (b2) after the step (b1), irradiating the first main surface of the semiconductor wafer with far-ultraviolet ray; and (b3) after the step (b2), applying a heat treatment to the semiconductor wafer. |
地址 |
Kawasaki-Shi, Kanagawa JP |