Watchdog Timer

摘要

A microcontroller may comprise a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further having logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer.

主权项

1. A watchdog timer unit configured to define a first and a second watchdog time period, wherein the watchdog timer unit is configured, after activation of the watchdog timer unit, to automatically select the first watchdog time period until a first clear watchdog signal has been received whereupon the watchdog timer unit switches to the second watchdog time period.