发明名称 |
MEMORY CONTROLLER, DATA STORAGE DEVICE, AND DATA WRITING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To efficiently transfer write data and parity data.SOLUTION: A memory controller comprises: queuing parts which queue a plurality of commands to a bank #1 and have flags respectively corresponding to the plurality of commands; a bank controller 11 which sequentially executes the plurality of commands; a data controller 12 which transfers write data to the bank #1 when a prescribed command to be executed among the plurality of commands is a write command to one of a plurality of physical addresses in the bank #1; and a parity controller 13 which generates parity data for restoring the write data, according to a value of a flag corresponding to the prescribed command, until the prescribed command is completed.SELECTED DRAWING: Figure 1 |
申请公布号 |
JP2016167210(A) |
申请公布日期 |
2016.09.15 |
申请号 |
JP20150047184 |
申请日期 |
2015.03.10 |
申请人 |
TOSHIBA CORP |
发明人 |
ICHISHIMA JUN;YOSHIDA KENJI;TAKAI YORIHARU;YAMAZAKI SUSUMU;TSUBOI NORIBUMI |
分类号 |
G06F12/16 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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