| 摘要 |
<p>In a cyclic analog-digital converter wherein an analog input signal sampled by a sample hold circuit is amplified by an operational amplifier and then the amplified signal is delivered to a comparator and is converted into digital data per internal processing cycle and predetermined bits of the digital data is output from an encoder, a bias current to be supplied to the operational amplifier from a bias circuit is reduced as the internal processing cycles advance in one conversion cycle. The number of the internal processing cycles in one conversion cycle is counted by a counter. Based on the counter value of the counter, a decoder outputsa signal for controlling the bias circuit in such a manner that the bias current may be reduced as the internal processing cycles advance in one conversion cycle.</p> |
