发明名称 |
Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device |
摘要 |
A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film ( 10 ) constituting the channel forming region from an n type poly-crystalline silicon film ( 7 ) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film ( 10 ); and reducing an effective impurity concentration in the poly-crystalline silicon film ( 10 ).
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申请公布号 |
US2007202638(A1) |
申请公布日期 |
2007.08.30 |
申请号 |
US20070790130 |
申请日期 |
2007.04.24 |
申请人 |
TABATA TSUYOSHI;NAKAZATO KAZUO;KUJIRAI HIROSHI;MONIWA MASAHIRO;MATSUOKA HIDEYUKI;KISU TERUAKI;KISU TERUO;KISU HARUKO;HAGA SATORU |
发明人 |
TABATA TSUYOSHI;NAKAZATO KAZUO;KUJIRAI HIROSHI;MONIWA MASAHIRO;MATSUOKA HIDEYUKI;KISU TERUAKI;KISU TERUO;KISU HARUKO;HAGA SATORU |
分类号 |
H01L21/84;H01L21/8242 |
主分类号 |
H01L21/84 |
代理机构 |
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