发明名称 PLL CIRCUIT AND CONTROL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To obtain an oscillation output signal at a desired oscillation frequency by securely preventing a PLL circuit from malfunctioning in a convergence stage of the oscillation frequency after power-on operation. <P>SOLUTION: The PLL circuit has a phase comparator 20 which detects the phase difference between a reference signal REF and a feedback signal FB; a loop filter 30A where electric charges are charged or discharged according to the phase difference; and a voltage-controlled oscillator 50A which oscillates the output signal at an oscillation frequency corresponding to an input voltage, based upon the amount of electric charges accumulated in the loop filter. In addition to these units, the PLL circuit includes a control circuit 40A which charges or discharges electric charges to and from the loop filter to vary the input voltage to a voltage within a specified range, and then controls the input voltage so that the oscillation frequency does not exceed an operable frequency of a frequency divider, thereby preventing the output signal from being oscillated at an oscillation frequency higher than the operable frequency of the frequency divider. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007104585(A) 申请公布日期 2007.04.19
申请号 JP20050295400 申请日期 2005.10.07
申请人 FUJITSU LTD 发明人 KIKUCHI KIYOHIKO;ANBUTSU HIDEAKI
分类号 H03L7/093;H03L7/08 主分类号 H03L7/093
代理机构 代理人
主权项
地址