| 摘要 |
The disclosure discloses a GOA circuit and a liquid crystal display. The GOA circuit comprises a plurality of GOA units, each sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region. The GOA unit comprises N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit. The pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the (N+1)th-staged horizontal scanning line is charged. By way of such configuration, the two-staged GOA units share a common pull-down holding circuit to further reduce the power consumption. |
| 主权项 |
1. A GOA circuit for a liquid crystal display, the GOA circuit comprising a plurality of GOA units, each of the GOA unit sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region, the GOA unit comprising N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit;
wherein the N-staged pull-up circuits and the pull-down holding circuit respectively connect to the Nth-staged gate signal point and the Nth-staged horizontal scanning line, and the N-staged pull-up control circuits and the N-staged pull-down circuits connected to the Nth-staged gate signal point; wherein the (N+1)-staged pull-up circuits and the pull-down holding circuit respectively connect to the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line, and the (N+1)-staged pull-up control circuits and the (N+1)-staged pull-down circuits connect to the (N+1)th-staged gate signal point; wherein the pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged; wherein the pull-down holding circuit comprises: a first transistor having a gate and a drain connected to a first clock signal; a second transistor having a gate connected to the source of the first transistor, a drain connected to the first clock signal, and a source connected too a first common point; a third transistor having a gate connected to the second clock signal, a drain connected to the first clock signal, and a source connected to the first common point; a fourth transistor having a gate and drain connected to the first common point; a fifth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the first transistor and the source of the fourth transistor, and a source connected to the first direct current low voltage; a sixth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the first transistor, and a source connected to the first direct current low voltage; a seventh transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged gate signal point, and a source connected to the first direct current low voltage; an eighth transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged horizontal scanning line and a source connected to the first direct current low voltage; a ninth transistor having a gate connected to a second common point, a drain connected to the (N+1)-staged gate signal point, and a source connected to the first direct current low voltage; a tenth transistor having a gate connected to the second common point, a drain connected to the (N+1)th-staged horizontal scanning line, and a source connected to the first direct current low voltage; an eleventh transistor having a gate and a drain connected to the second clock signal; a twelfth transistor having a gate connected to the source of the eleventh transistor, a drain connected to the second clock signal, and a source connected to the second common point; a thirteenth transistor having a gate connected to the first clock signal, a drain connected to the second clock signal, and a source connected to the second common point; a fourteenth transistor having a gate and a drain connected to the second common point; a fifteenth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the eleventh transistor and the source of the fourteenth transistor, and a source connected to the first direct current low voltage; a sixteenth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the eleventh transistor, and a source connected to the first direct current low voltage; a seventh transistor having a gate connected to the second common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage; an eighteenth transistor having a gate connected to the second common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage; a nineteenth transistor having a gate connected to the first common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage; and a twentieth transistor having a gate connected to the first common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage; wherein the GOA unit further comprises a reset circuit connected to the Nth-staged gate signal point, the (N+1)th-staged gate signal point and the first direct current low voltage, for pulling down the voltage level of the Nth-staged gate signal point and the (N+1)th-staged gate signal point to the low voltage level after a reset signal is received. |
