发明名称 Negative level shifter
摘要 A level shifter including a differential input stage including first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller including third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal, and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage is disclosed. A bias voltage applied to bulks or bodies of the first through the fourth transistors equals or substantially equals the first voltage.
申请公布号 US9024674(B1) 申请公布日期 2015.05.05
申请号 US201414150590 申请日期 2014.01.08
申请人 Dongbu HiTek Co., Ltd. 发明人 Kim Jong Cheol
分类号 H03L5/00;H03K19/0175;H03K19/0185 主分类号 H03L5/00
代理机构 Central California IP Group, P.C. 代理人 Fortney Andrew D.;Central California IP Group, P.C.
主权项 1. A level shifter comprising: a differential input stage comprising first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller comprising third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal; and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage, wherein a bias voltage applied to a bulk of each of the first and second transistors is a third voltage, the first voltage is a ground voltage, the second and third voltages are first and second negative voltages, respectively, and the third voltage has a lower absolute value than the second voltage.
地址 Bucheon-si KR