Semiconductor memory component, such as multiport SRAM cell with two word lines and CMOS structure

摘要

In the cell are formed two P-trough regions at both sides of an N-trough region. The boundaries between the P-trough regions and the N-trough region extend parallel to bit lines (BL00, BL10, BLL11). In each P-trough region are formed two access gates. There are two CMOS interverters, the first one with first N-channel MOS transistor (N1). A first P-channel MOS transistor (P1), and inputs and outputs. The second inverter contains a second P-channel MOS transistor (P2), a second N-channel MOS transistor (N2), and inputs and outputs. The entire cell circuitry is specified.