发明名称 Wide band deterministic interface
摘要 A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.
申请公布号 US9042431(B1) 申请公布日期 2015.05.26
申请号 US200912391712 申请日期 2009.02.24
申请人 Altera Corporation 发明人 Yadavalli Venkat;Krishnamurthy Sridhar;Orlando Gerardo;King David Richardson;Clauss Ken;Krumpoch Mark;Markou Peter
分类号 H04B1/38;H04L1/24;H04L1/00 主分类号 H04B1/38
代理机构 Weaver Austin Villeneuve & Sampson LLP 代理人 Weaver Austin Villeneuve & Sampson LLP
主权项 1. A method, comprising: compensating for non-deterministic data processing time in a transceiver, for a plurality of operation frequencies, the transceiver comprising a receiver circuitry having variable latency components including a deserializer, a transmitter circuitry including a serializer, a delay calibration logic (DCL), the DCL being communicatively coupled between an output of the receiver circuitry and an input of the transmitter circuitry, and a feedback path configured to be switchable by the DCL between an open state and a closed state, said compensating including for each transceiver operation frequency, sending test data over the feedback path while the feedback path is in the closed state; and, with the DCL: measuring a plurality of travel times for the test data;determining, from the plurality of travel times, a compensation delay that provides a constant deterministic delay for the transceiver;opening the feedback path; andadding the compensation delay to input data received at the transceiver; wherein the DCL comprises a calibration control logic, and a plurality of pipelines for processing a plurality of parallel data lines, the calibration control logic being disposed between the output of the receiver circuitry and the plurality of pipelines.
地址 San Jose CA US