| 摘要 |
A data processing apparatus and method are provided for handling write access requests to shared memory. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with each processing unit having a cache associated therewith for storing a subset of the data for access by that processing unit. Cache coherency logic is provided that employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. Each processing unit will issue a write access request when outputting a data value for storing in the shared memory, and when the write access request is of a type requiring both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is then performed in respect of all of the caches associated with the plurality of processing units, including the cache associated with the processing unit that issued the write access request, in order to ensure that the data in those caches is kept coherent. The cache coherency logic is further operable to issue an update request to the shared memory in respect of the data value the subject of the write access request. Such a technique provides a particularly simple and efficient mechanism for ensuring the correct behaviour of such write access requests, without impacting the complexity and access timing of the originating processing unit and its associated cache.
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