LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION

摘要

A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

主权项

1. A method comprising:
in a device including a controller, the controller including a root detection circuit having multiple sets of multipliers, performing:
configuring the root detection circuit according to a degree of a polynomial; andin response to detection of a root of multiple roots of the polynomial, modifying a configuration of the root detection circuit based on a polynomial degree reduction (PDR) scheme.