发明名称 |
Method and mechanism for verifying and simulating power aware mixed-signal electronic designs |
摘要 |
Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs. |
申请公布号 |
US9058440(B1) |
申请公布日期 |
2015.06.16 |
申请号 |
US200912638493 |
申请日期 |
2009.12.15 |
申请人 |
Cadence Design Systems, Inc. |
发明人 |
Kolpekwar Abhijeet |
分类号 |
G06F17/50;G06G7/62;G06G7/54 |
主分类号 |
G06F17/50 |
代理机构 |
Vista IP Law Group, LLP |
代理人 |
Vista IP Law Group, LLP |
主权项 |
1. A computer implemented method using a computer processor for simulating a mixed signal electronic design, comprising:
using at least the computer processor to perform a process, the process comprising: receiving the mixed signal electronic design for simulation, wherein
the mixed signal electronic design is associated with power state information that includes a plurality of states of a power domain of at least a portion of the mixed signal electronic design; inserting a power aware interface element, which is made aware of information or data about power management for the mixed signal electronic design, between a digital design portion and an analog design portion based at least in part upon the power state information of a driving part or a driven part of the digital design portion and the analog design portion, rather than based on whether or not a net transitions between the digital design portion and the analog design portion, wherein
the power aware interface element performs conversion of an electrical signal between a digital domain and an analog domain based at least in part upon the power state information; and using the power aware interface element to simulate the mixed signal electronic design. |
地址 |
San Jose CA US |