| 摘要 |
Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout design for the layer then is divided into separate areas or "windows," and a target density for each window is determined. More particularly, each window is analyzed to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. In some implementations, the target density will be the smallest density that will comply with each of the specified density value constraints. Once the target density for the window has been determined, the fill polygons required to most closely approach this target density are selected and added to the circuit layout design. With some implementations, this process may be repeated for fill polygons of different sizes or shapes.
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