| 主权项 |
1. A node comprising:
a memory storing a sequence of instructions; and a hardware processor operable to execute the sequence of instructions to encode data according to a Low Density Parity Check (LDPC) matrix, the encoded data corresponding to a code word comprising a payload and a parity, the payload length being the product of a first number and a second number, the parity length being the product of the first number and a third number, the LDPC matrix comprising:
a) a systematic portion having a plurality of systematic elements having a value, the systematic portion having the second number of columns and the third number of rows, each systematic element having a value equal to zero corresponding to an identity submatrix, the value of each positive systematic element determining a cyclic shift to be applied to rows of the identity submatrix, each positive systematic element corresponding to a shifted identity matrix element, the identity submatrix having the first number of columns and the first number of rows, each negative systematic element corresponding to a zero submatrix having the first number of columns and the first number of rows; andb) a parity portion having a plurality of parity elements having a value, the parity portion having the third number of columns and the third number of rows, each parity element having a value equal to zero corresponding to the identity submatrix, the value of each positive parity element determining a cyclic shift to be applied to rows of the identity submatrix, each positive parity element corresponding to a shifted identity matrix element, two or more columns of the parity portion having an equal number of positive parity elements, the equal number of positive elements being one or more positive elements, each negative parity element corresponding to the zero submatrix. |
