PROGRAMMABLE FORWARDING PLANE

摘要

A forwarding plane comprising a scalable array of field programmable gate array (FPGA) devices, a memory bank, FPGA data and transport network ports, and an array interconnect. The scalable array is configured to execute a networking application source code partitioned as computing elements executed by the FPGA devices with a uniform global memory address space. The memory bank includes an allocated portion of the FPGA devices addressable by the address space. The ports are coupled to data networks and include ingress ports configured to receive traffic and egress ports configured to transmit traffic. The array interconnect is configured to forward the traffic from the ingress ports to the egress ports, choose cell sizes of data cells that encapsulate payload data units of the traffic, control latency between the FPGA devices based on the chosen cell sizes; and enable utilization of the memory bank for buffering of the traffic.

主权项

1. A forwarding plane comprising:
a scalable array of field programmable gate array (FPGA) devices that is configured to execute a networking application source code that is partitioned among the FPGA devices as a plurality of computing elements executed by the FPGA devices with a uniform global memory address space; a memory bank that includes an allocated portion of one or more of the FPGA devices, wherein the memory bank is addressable by the uniform global memory address space; FPGA data and transport network ports that are configured to be coupled to one or more data networks, wherein the FPGA data and transport network ports include one or more ingress ports that are configured to receive traffic and egress ports that are configured to transmit traffic; and an array interconnect that is included in the scalable array, wherein the array interconnect is configured to:
forward the traffic received at the ingress ports to the egress ports;choose one or more maximum cell sizes of data cells that are configured to encapsulate payload data units (PDUs) of the traffic received at the ingress ports;control latency between the FPGA devices based on the chosen cell sizes; andenable utilization of the memory bank by the FPGA devices for buffering of a portion of the traffic.