发明名称 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
摘要 A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
申请公布号 US2009059703(A1) 申请公布日期 2009.03.05
申请号 US20080172108 申请日期 2008.07.11
申请人 HYNIX SEMICONDUCTOR, INC. 发明人 HWANG TAE JIN;KIM YONG JU;SONG HEE WOONG;OH IC SU;KIM HYUNG SOO;CHOI HAE RANG;LEE JI WANG
分类号 G11C7/00 主分类号 G11C7/00
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