| 摘要 |
A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation. |
| 主权项 |
1. A device comprising:
a plurality of terminals supplied with command information from an outside of the device, the command information comprising a plurality of bits respectively corresponding to the plurality of terminals, and the plurality of bits being configured to take a plurality of combinations in a logic level to designate a plurality of commands; and an internal circuit coupled to the plurality of terminals to receive the command information, the internal circuit being configured to perform a first operation responsive to a first one of the plurality of combinations in the logic level when the internal circuit is in a first mode and to perform a second operation responsive to the first one of the plurality of combinations in the logic level when the internal circuit is in a second mode, the first operation being different from the second operation, and the first mode being different from the second mode. |
