CLOCK SIGNAL GENERATING CIRCUIT, GATE DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

摘要

A clock signal generating circuit, a gate driving circuit, a display panel and a display device are disclosed. A first clock signal terminal inputs a first clock signal to a selection module. A second clock signal terminal inputs a second clock signal to the selection module. The selection module couples a high level signal input terminal to an output terminal or disconnects the high level signal input terminal from the output terminal according to the first clock signal, and couples a low level signal input terminal to the output terminal or disconnects the low level signal input terminal from the output terminal according to the second clock signal. The selection module couples the high level signal input terminal and the low level signal input terminal alternately to the output terminal, so that the output terminal outputs a target clock signal.

主权项

1. A clock signal generating circuit, comprising a selection module, a high level signal input terminal, a low level signal input terminal, a first clock signal terminal, a second clock signal terminal and an output terminal, wherein
the first clock signal terminal inputs a first clock signal to the selection module; the second clock signal terminal inputs a second clock signal to the selection module; the selection module couples the high level signal input terminal to the output terminal or disconnects the high level signal input terminal from the output terminal according to the first clock signal, and couples the low level signal input terminal to the output terminal or disconnects the low level signal input terminal from the output terminal according to the second clock signal; and the selection module couples the high level signal input terminal and the low level signal input terminal alternately to the output terminal, so that the output terminal outputs a target clock signal.