发明名称 |
Calibration circuit, semiconductor device including the same, and data processing system |
摘要 |
A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.
|
申请公布号 |
US2009009213(A1) |
申请公布日期 |
2009.01.08 |
申请号 |
US20080213962 |
申请日期 |
2008.06.26 |
申请人 |
ELPIDA MEMORY, INC. |
发明人 |
OSANAI FUMIYUKI;FUJISAWA HIROKI |
分类号 |
H03K19/003 |
主分类号 |
H03K19/003 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|