发明名称 CALCULATING CIRCUIT-LEVEL LEAKAGE USING THREE DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN AND A REDUCED NUMBER OF TRANSISTORS
摘要 A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.
申请公布号 US2016210387(A1) 申请公布日期 2016.07.21
申请号 US201615051334 申请日期 2016.02.23
申请人 International Business Machines Corporation 发明人 JOSHI RAJIV V.;Kim Keunwoo
分类号 G06F17/50;G01R31/28;G01R31/26 主分类号 G06F17/50
代理机构 代理人
主权项 1. A computer readable storage device containing an executable program for calculating leakage of a circuit comprising a plurality of transistors, where the program performs steps comprising: generating a leakage model of the circuit using a three-dimensional device simulation tool, wherein the only transistors simulated by the leakage model are those of the plurality of transistors that are positioned along a leakage path in the circuit; measuring in the leakage model a leakage across each of the transistors simulated by the leakage model; and calculating the leakage of the circuit by summing the leakage across each transistor simulated by the leakage model, as measured in the leakage model.
地址 Armonk NY US