Device and method for synchronization in a mobile communication system

摘要

Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.

主权项

1. A controller device for a data interface between sub-systems in a chain of at least two sub-systems in a mobile communication base station system, the sub-systems comprising at least one second sub-system and at least one first sub-system for controlling the second sub-system, at least one first sub-system being a synchronization master controlling a time synchronization of the sub-systems, the controller device comprising:
a clock input for receiving a reference clock; a sync input for receiving an external synchronization signal; a tracking clock circuit connected to the clock input and the sync input, for generating a transmit clock based on the reference clock signal and the synchronization signal, the tracking clock circuit comprising:
a controllable phase locked loop, (PLL), for generating the transmit clock, the PLL comprising a PLL output for outputting the transmit clock, a first phase input coupled to the reference clock and a second phase input coupled to the PLL output via a negative feedback loop; anda frequency and phase tracking loop coupling the sync input and the second phase input to a control input of the controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase error between the external synchronization signal and the feedback signal; and a transmitter for transmitting binary data from the first sub-system to the second subsystem, the binary data having a bit duration controlled by a clock cycle of the transmit clock, and the transmitter being connected with a clock input to the PLL output for clocking the transmitter with the transmit clock.