| 摘要 |
A DLL(Delay Locked Loop) circuit is provided to support stable data output operation of a semiconductor integrated circuit by making uniform phase of a rising clock and a falling clock. A phase splitter(30) generates a rising clock and a falling clock by controlling the phase of a delay clock. An amplification unit(40) generates a rising amplification clock and a falling amplification clock by amplifying the rising clock and the falling clock differentially in response to a first and a second duty control signal. A duty cycle control unit(50) generates the first and the second duty control signal by sensing duty ratio of the rising amplification clock and the falling amplification clock. The amplification unit makes a first period of the rising amplification clock narrow if the potential level of the first duty control signal is higher than the potential level of the second duty control signal, and makes the first period of the falling amplification clock narrow if the potential level of the first duty control signal is lower than the potential level of the second duty control signal.
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