发明名称 ANALOG-DIGITAL CONVERTER AND APPARATUS FOR CONCEALING PACKET LOSS
摘要 An analog to digital converter using a delay locked loop and an analog to digital converting method are provided to reduce difference between the delay due to the analog input signal and the delay of the reference signal converting a digital code to analog code by using a successive approximation method and a delay locked loop. A first delay unit(10) receives a first clock signal and delays the first clock signal as much as the first delay time according to the analog input signal. A second delay unit(20) delays the first clock signal as much as the second delay time according to the reference signal converting the N bit digital signal to the analog signal. The N is a positive integer. A compensation unit(300) generates the N bit digital bit to reduce the difference between the first delay time and the second delay time and supplies the reference signal by converting the N bit digital signal to the analog signal. The compensation unit includes a delay error compensation unit and a digital to analog converter.
申请公布号 KR20090063951(A) 申请公布日期 2009.06.18
申请号 KR20070131490 申请日期 2007.12.14
申请人 IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY) 发明人 YOO, CHANG SIK;SEOK, JI HWAN
分类号 H03M1/12 主分类号 H03M1/12
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