POWER REDUCTION THROUGH CLOCK MANAGEMENT

摘要

Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

主权项

1. A slave device, comprising:
an audio component comprising an analog component; a communication bus interface configured to couple to a communication bus and receive a clock signal therefrom; a frequency divider configured to receive the clock signal from the communication bus interface; and a control system operatively coupled to the frequency divider, the control system configured to:
determine a frequency requirement for the analog component;instruct use of the frequency divider to divide the clock signal from the communication bus interface to meet the frequency requirement; andarrange for the analog component to receive the divided clock signal.