| 摘要 |
A NOR gate circuit, a shift register, an array substrate and a display device. The NOR gate circuit comprises a first inverter (11) and a second inverter (12); the first inverter (11) and the second inverter (12) both have an input end (VIN), a high-voltage end (VGH), a low-voltage end (VGL) and an output end (VOUT); and the output end (VOUT) of the first inverter (11) is connected to the high-voltage end (VGH) of the second inverter. At least one of the first inverter and the second inverter comprises a first transistor (T1; T5), wherein a grid electrode of the first transistor (T1; T5) is connected to a first node (VA), a first electrode is connected to the high-voltage end (VGH), and a second electrode is connected to the output end (VOUT); a first capacitor (C1; C2), wherein a first end of the first capacitor (C1; C2) is connected to the first node (VA), and a second end is connected to the output end (VOUT); a pull-up module (12a) for pulling up the potential of the first node (VA) by using the potential at the high-voltage end (VGH) when the high-voltage end (VGH) is at a high level; and a pull-down module (12b) for pulling down the potential of the first node (VA) and the output end (VOUT) by using the potential at the low-voltage end (VGL) under the control of a signal received by the input end (VIN). The deficiency of threshold loss existing in a NOR gate circuit formed by oxide TFTs is eliminated. |
