发明名称 |
CIRCUIT LAYOUT METHODOLOGY |
摘要 |
A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
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申请公布号 |
US2006195809(A1) |
申请公布日期 |
2006.08.31 |
申请号 |
US20050906591 |
申请日期 |
2005.02.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COHN JOHN M.;HIBBELER JASON;STAMPER ANTHONY K.;RANKIN JED H. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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