| 摘要 |
PROBLEM TO BE SOLVED: To make signal delay short, when the load capacity at an output terminal is large, and to shorten the time for which the output terminal stays at an intermediate potential. SOLUTION: A 1st inverter 10 outputs two different signals to a point A and to a point B, according to an input signal IN. A 2nd inverter 20 inputs the two signals outputted from the 1st inverter 10 and outputs an output signal OUT according to both the input signals. A variable resistance element VR1 has its resistance value controlled to vary, according to the value of the output signal (output voltage) OUT of the 2nd inverter 20. Namely, the output signal OUT of the variable resistance element VR1, while having a large resistance value at potentials close to a source voltage VDD and a ground voltage VSS, has a small resistance value, at intermediate potentials between the source voltage VDD and ground voltage VSS. COPYRIGHT: (C)2005,JPO&NCIPI
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