| 发明名称 |
VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS |
| 摘要 |
In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W. |
| 申请公布号 |
US2016219225(A1) |
申请公布日期 |
2016.07.28 |
| 申请号 |
US201514603354 |
申请日期 |
2015.01.22 |
| 申请人 |
GOOGLE INC. |
发明人 |
Zhu Qiuling;Shacham Ofer;Redgrave Jason Rupert;Finchelstein Daniel Frederic;Meixner Albert |
| 分类号 |
H04N5/262 |
主分类号 |
H04N5/262 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S; and a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL, the linebuffer including:
a full-size buffer having a width of W and a height of (S−1); anda sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W. |
| 地址 |
Mountain View CA US |
