发明名称 情報処理装置の制御方法、制御プログラム、情報処理装置
摘要 A method of controlling an apparatus including a processor including a plurality of cores, the method includes, when a number of the cores to be activated is M, determining whether or not a first power consumed by the M activated core is within a range of a second power to be consumed when the number of the cores to be activated is M+N, and when the first power is out of the range of the second power, prohibiting to increase the number of the cores to be activated from M to M+N.
申请公布号 JP6051924(B2) 申请公布日期 2016.12.27
申请号 JP20130032663 申请日期 2013.02.21
申请人 富士通株式会社 发明人 村上 岳生
分类号 G06F1/32;G06F1/04;G06F1/26;G06F9/50 主分类号 G06F1/32
代理机构 代理人
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