Element isolation structure of a semiconductor device to suppress reduction in threshold voltage of parasitic MOS transistor

摘要

A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.